Integrated circuits (ICs) typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring typically connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring above the semiconductor portion of the substrate are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the substrate and conductive vias run perpendicular to the substrate; the conductive vias typically interconnect the different levels of the metal wiring levels.
Two developments in the last decade have contributed to increased performance of contemporary ICs. One such development is the use of copper Cu as the interconnect metal of the BEOL interconnect structure. Copper is advantageous because it has a higher conductivity compared with the other traditionally used interconnect metals, such as, for example, aluminum Al.
A second development is the employment within the BEOL interconnect structure of a low dielectric constant (low k) dielectric material as the interlevel dielectric (ILD) layers. By “low k”, it is meant a dielectric material whose dielectric constant is less than silicon dioxide. The low k dielectric alternatives may be non-porous, porous or a combination of porous and non-porous.
When copper Cu is used as the metal in the interconnect wiring layers, a dielectric barrier layer or “dielectric cap” is typically required between the copper features and the ILD to prevent copper from diffusing into certain types of ILD materials so as to prevent the copper from damaging the electrical properties of the dielectric.
Under certain circumstances, semiconductor chips may be subjected to external stresses, either during the manufacture or packaging of the chips, or when the packaged chips are mounted or installed in an electronic system for subsequent use. Occasionally, such external stresses can cause cracking and delamination of dielectric materials and metal films embedded in the dielectric materials. Difficulties reside in finding appropriate materials and manufacturing processes which permit copper metal lines to be utilized in certain types of low k dielectric materials, particularly when high stress conditions are present.
Currently, SiCNxH films are used as the dielectric barrier layer or “dielectric cap” in 90 nm complementary metal oxide semiconductor (CMOS) electronic devices. For Cu-containing interconnect structures in nano integrated circuit devices, a requirement for the next generations of device technology entails a significant reduction in the capacitance of the dielectric barrier layer compared to existing SiCNxH films.
Prior art SiCNxH films are good Cu cap layers despite having a dielectric constant between 5.0 and 5.5 and a high capacitance. Furthermore, the stress of prior art SiCNxH films changes from compressive to tensile under subsequent post processing steps such as, for example, UV curing or E-beam curing of the ILD dielectrics. This change in stress of prior art SiCNxH films under subsequent post processing steps causes significant cracking and thus limits the use of SiCNxH films.
In view of the above, there is a need for providing a dielectric barrier layer, i.e., dielectric cap, that has a lower dielectric constant than existing SiCNxH films, and maintains a compressive stress even under subsequent post deposition processing.